Description

Product details

C Compiler optimized architecture/instruction set Data EEPROM to 1024 bytes Linear program memory addressing to 64 Kbytes Linear data memory addressing to 4 Kbytes Up to 16 MIPS operation 16-bit wide instructions, 8-bit wide data path Priority levels for interrupts 31-level, software accessible hardware stack 8 x 8 Single-Cycle Hardware Multiplier Sleep mode: 100 nA, typical Watchdog Timer: 500 nA, typical Timer1 Oscillator: 500 nA @ typical 32 kHz Flexible Oscillator Structure Factory calibrated to ± 1% Software selectable frequencies range of 31 kHz to 16 MHz 64 MHz performance available using PLL no external components required Four Crystal modes up to 64 MHz Two external Clock modes up to 64 MHz

Keywords

• ±
• PLL
• 500 nA
• 100 nA
• 16 MHz
• 64 Kbytes
• 31 kHz to
• interrupts
• Data EEPROM
• Watchdog Timer
• Priority levels
• Timer1 Oscillator
• PT MCP C Compiler
• Linear data memory
• 64 MHz performance
• Four Crystal modes
• external components
• 8-bit wide data path
• Up to 16 MIPS operation
• 16-bit wide instructions
• Two external Clock modes
• architecture/instruction set
• 1024 bytes Linear program memory
• Software selectable frequencies range
• 31-level, software accessible hardware stack
• 8 x 8 Single-Cycle Hardware Multiplier Sleep mode
• typical 32 kHz Flexible Oscillator Structure Factory